Changelog
2024-03-14
- Added testbench outputs to Verilog modules
- Added SPI module description
- Reset signal was added to the registers module, required because SPI clock isn't free-running.
- Added instructions for connecting to mainboard through SPI
- Fixed broken links here and in Development/Testing
- Fixed command for running tests in Development/Testing (missing asterisks)
- Published tests results as part of Task 7. Implement SPI TPM protocol
- Updated FPGA utilisation numbers
2024-01-16
- Added page about running tests
- Published tests results as part of Task 6. Base tests
- Small changes to description of interrupts handling
2023-11-26
- Reduce numbers of bi-directional lines to minimum (Yosys doesn't like them)
- Switch to OrangeCrab
- Reason
- Updated building instructions - actual instructions moved to README in top level repository to avoid duplications
- Modified memory map
- New FPGA utilization numbers
- Instructions for connecting TwPM to mainboard - Protectli VP46xx
- Description of new modules (NEORV32, LiteDRAM, TPM buffer)
2023-07-31
Added
- Blog post on optimizing SPI communitation on STM32
- Information on maximum real SPI frequency on STM32 in the hardware selection section
2023-05-24
Added
- New Verilog Module specification in Development section, added graphics and links to modules' code
- Fixed broken links in changelog (here) and Development section
- First implementation details documented
- Update statuses on the roadmap